AD9523 PLL Configuration for Phase‑Aligned Multi‑Channel Outputs in the AERIS‑10 Radar

The AD9523‑1 clock generator uses dual PLLs with zero‑delay mode and synchronous startup sequencing to produce deterministic, phase‑aligned clocks for all 16–32 radar channels.

The AD9523‑1 is the timing backbone of the AERIS‑10 radar system developed in the NawfalMotii79/PLFM_RADAR repository. This high‑performance clock generator produces stable, low‑jitter reference clocks that synchronize every downstream component—from the ADF4382 frequency synthesizers to the FPGA, DAC, and ADC. Proper AD9523 PLL configuration for phase‑aligned multi‑channel outputs ensures coherent beamforming across all phase‑shifter channels by maintaining deterministic phase relationships throughout the entire signal chain.

Clock Tree Architecture and Distribution

The AERIS‑10 radar implements a centralized clocking strategy where the AD9523 drives multiple outputs through a carefully planned distribution network.

Key clock destinations include:

• OUT6 → 100 MHz system clock for STM32 MCU and FPGA
• OUT11 → 120 MHz DAC clock for the DAC chip (U3)
• Additional outputs → ADC reference and FPGA MMCM inputs

The system diagram in docs/architecture.html illustrates how these outputs feed directly into the FPGA, DAC, and ADC while maintaining a single timing domain critical for coherent operation.

Dual‑PLL Configuration for Multi‑Frequency Operation

The AD9523 contains two independent PLLs, each optimized for different clocking requirements as defined in 9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ad9523.h.

PLL1: 100 MHz System Clock

PLL1 generates the primary system reference that synchronizes the STM32 microcontroller and FPGA logic. This clock establishes the common timebase for all control operations and digital signal processing.

Critical configuration elements for phase alignment:

Register	Purpose	Value
AD9523_PLL1_REF_CTRL	Enable reference input	0x04
AD9523_PLL1_FEEDBACK_DIVIDER	Set loop divider	0x17
AD9523_PLL1_ZERO_DELAY_MODE_INT	Enable zero‑delay mode	0x01

The zero‑delay mode (AD9523_PLL1_ZERO_DELAY_MODE_INT = 0x01) is essential for phase‑aligned outputs. This configuration ensures that the output clock edge has a deterministic, near‑zero phase offset relative to the reference input.

PLL2: 120 MHz DAC Clock

PLL2 produces the high‑frequency clock required by the DAC chip (U3). This clock is subsequently cleaned by the FPGA MMCM for jitter reduction.

Key PLL2 registers include:

• AD9523_PLL2_CTRL – PLL2 enable control
• AD9523_PLL2_FEEDBACK_DIVIDER_AB – Combined divider setting (0xF1)
• AD9523_PLL2_LOOP_FILTER_CTRL – Loop filter configuration

Both PLLs derive their outputs from the same internal VCO distribution network, ensuring that phase relationships remain fixed regardless of temperature or voltage variations.

Synchronous Startup Sequence for Phase Alignment

The MCU firmware in 9_Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp implements a strict initialization sequence that forces both PLLs to lock simultaneously. This phase‑aligned startup is critical for coherent beamforming across all 16 or 32 channels.

/* Initialise AD9523 – reset, select reference, then release */
AD9523_RESET_ASSERT();               // hold reset low
HAL_Delay(10);
AD9523_REF_SEL(true);                // select external reference
AD9523_RESET_RELEASE();              // release reset, start PLLs

/* Configure PLL1 (100 MHz system clock) */
uint8_t pll1_cfg[] = {
    AD9523_PLL1_REF_CTRL,  0x04,      // enable reference
    AD9523_PLL1_FEEDBACK_DIVIDER, 0x17,
    AD9523_PLL1_ZERO_DELAY_MODE_INT, 0x01,
    /* additional PLL1 registers … */
};
ad9523_write_bulk(pll1_cfg, sizeof(pll1_cfg));

/* Configure PLL2 (120 MHz DAC clock) */
uint8_t pll2_cfg[] = {
    AD9523_PLL2_CTRL, 0x01,          // enable PLL2
    AD9523_PLL2_FEEDBACK_DIVIDER_AB, 0xF1,
    AD9523_PLL2_LOOP_FILTER_CTRL, 0x01,
    /* additional PLL2 registers … */
};
ad9523_write_bulk(pll2_cfg, sizeof(pll2_cfg));

/* Trigger a synchronous pulse on both PLLs */
AD9523_SYNC_PULSE();                 // forces both PLLs to lock together

The AD9523_SYNC_PULSE() function assertion triggers simultaneous locking of both PLLs, eliminating relative phase wander between the system clock and DAC clock during startup.

FPGA Clock Constraints and Routing

The Xilinx XDC constraints file 9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc maps AD9523 outputs to dedicated clock-capable pins on the xc7a200t device:

• MRCC (Multi-Region Clock Capable) banks receive the 100 MHz and 120 MHz outputs
• PLL lock status is monitored by FPGA logic for system health verification
• MMCM instantiation in the FPGA provides additional jitter cleaning of the 120 MHz DAC clock

These constraints ensure that the phase‑aligned clocks propagate through the FPGA with minimal skew and proper utilization of dedicated clock routing resources.

Output Divider and Zero‑Delay Implementation

Phase alignment across multiple channels relies on two AD9523 features working together:

1. Common VCO source – All outputs derive timing from a single voltage-controlled oscillator, eliminating VCO-to-VCO phase uncertainty

2. Zero‑delay mode per channel – Individual output channels configured with AD9523_PLL1_ZERO_DELAY_MODE_INT maintain deterministic phase relative to the reference

The AD9523's zero‑delay mode internally adjusts the feedback path so that the output clock edge aligns with the reference input edge. When applied to multiple outputs, this creates a phase‑locked network where all channels share identical timing.

Verification and Bring‑Up

The docs/bring-up.html documentation includes AD9523 status verification as a critical system checkout step:

• Verify PLL1 lock status via register readback or STATUS pin
• Confirm PLL2 lock before enabling DAC operation
• Measure phase relationship between outputs using oscilloscope or FPGA TDC

These diagnostics ensure that the phase‑aligned multi‑channel outputs meet specifications before radar calibration begins.

Summary

• The AD9523‑1 provides dual‑PLL clock generation with zero‑delay mode for deterministic phase alignment
• PLL1 (100 MHz) synchronizes the MCU and FPGA; PLL2 (120 MHz) clocks the DAC
• Synchronous startup via AD9523_SYNC_PULSE() forces simultaneous PLL locking
• Register configurations in ad9523.h and firmware in main.cpp implement the complete initialization sequence
• FPGA constraints ensure proper clock routing through MRCC pins to MMCM resources
• Phase alignment is maintained from RF front‑end through digital processing, enabling coherent 16–32 channel beamforming

Frequently Asked Questions

How does zero‑delay mode achieve phase alignment in the AD9523?

Zero‑delay mode configures the PLL feedback path so that the output clock edge aligns directly with the reference input edge. When multiple outputs are enabled with this mode, they all maintain the same phase relationship to the common reference, eliminating relative timing skew between channels.

Why does the AERIS‑10 radar use two PLLs instead of one?

The dual‑PLL architecture allows independent optimization for different frequency requirements. PLL1 generates a clean 100 MHz system clock for digital logic, while PLL2 produces the higher 120 MHz DAC clock with appropriate loop filter settings for the specific jitter requirements of the analog conversion stage.

What happens if the AD9523 PLLs do not lock simultaneously?

Non‑simultaneous locking introduces indeterminate phase offsets between the system clock and DAC clock. This degrades coherent beamforming performance because the phase relationship between chirp generation (DAC) and signal processing (FPGA) becomes unpredictable. The AD9523_SYNC_PULSE() function prevents this by forcing deterministic lock alignment.

How is PLL lock status verified in the AERIS‑10 firmware?

The firmware monitors the AD9523 STATUS pins and/or reads the lock detect register bit. The main.cpp HAL wrappers include functions to check PLL1 and PLL2 lock status before releasing the system for normal operation. The XDC constraints also route status signals to FPGA logic for continuous monitoring.

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